 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| w wm8150 single channel 12-bit cis/ccd afe with 4-bit wide output wolfson microelectronics plc w :www.wolfsonmicro.com production data, february 2005, rev 4.1 copyright ? 2005 wolfson microelectronics plc description the wm8150 is a 12-bit analogue front end/digitiser ic which processes and digitises the analogue output signals from ccd sensors or contact image sensors (cis) at pixel sample rates of up to 8msps. the device includes a complete analogue signal processing channel containing reset level clamping, correlated double sampling, programmable gain and offset adjust functions. internal multiplexers allow fast switching of offset and gain for line-by-line colour processing. the output from this channel is time multiplexed into a high-speed 12-bit analogue to digital converter. the digital output data is available in 4-bit wide multiplexed format. an internal 4-bit dac is supplied for internal reference level generation. this may be used to reference cis signals or during reset level clamping to clamp ccd signals. an external reference level may also be supplied. adc references are generated internally, ensuring optimum performance from the device. using an analogue supply voltage of 5v, a digital core voltage of 5v, and a digital interface supply of either 5v or 3.3v, the wm8150 typically only consumes 160mw when operating from a single 5v supply. features ? 12-bit adc ? 8msps conversion rate ? low power - 170mw typical ? 5v single supply or 5v/3.3v dual supply operation ? single channel operation ? correlated double sampling ? programmable gain (8-bit resolution) ? programmable offset adjust (8-bit resolution) ? programmable clamp voltage ? 4-bit wide multiplexed data output format ? internally generated voltage references ? 20-pin ssop package ? serial control interface applications ? flatbed and sheetfeed scanners ? usb compatible scanners ? multi-function peripherals ? high-performance ccd sensor interface block diagram vrlc/vbias vinp sen vsmp mclk sdi sck timing control cl rlc v s r s vrx vrt vrb cds 4 configurable serial control interface 12- bit adc agnd1 dgnd avdd dvdd1 op[0] op[1] op[2] op[3]/sdo agnd2 vref/bias r g b m u x r g b pga i/p signal polarity adjust 8 8 + + m u x data i/o port dvdd2 w wm8150 offset dac rlc dac
wm8150 production data w pd rev 4.1 february 2005 2 table of contents table of contents .........................................................................................2 pin configuration...........................................................................................3 ordering information ..................................................................................3 pin description ................................................................................................4 absolute maximum ratings.........................................................................5 recommended operating conditions .....................................................5 electrical characteristics ......................................................................6 input video sampling ............................................................................................. 8 output data timing ................................................................................................ 8 serial interface ..................................................................................................... 9 device description .......................................................................................10 introduction.......................................................................................................... 10 input sampling ....................................................................................................... 10 reset level clamping (rlc) ............................................................................... 10 cds/non-cds processing ................................................................................... 11 offset adjust and programmable gain....................................................... 12 adc input black level adjust .......................................................................... 13 overall signal flow summary ........................................................................ 13 calculating output for any given input .................................................... 13 output data format............................................................................................ 15 control interface .............................................................................................. 16 timing requirements ........................................................................................... 16 programmable vsmp detect circuit ............................................................. 17 references............................................................................................................. 18 power supply ........................................................................................................ 18 power management ............................................................................................. 18 operating modes .................................................................................................. 18 operating mode timing diagrams ................................................................... 19 device configuration .................................................................................21 register map .......................................................................................................... 21 register map description ................................................................................. 22 recommended external components........................................................... 24 package dimensions ....................................................................................25 important notice ..........................................................................................26 address:................................................................................................................... 26 production data wm8150 w pd rev 4.1 february 2005 3 pin configuration wm8150 1vinp 2 3 4 5 6 7 8 10 9 20 19 18 17 16 15 14 13 11 12 dvdd1 vsmp mclk dgnd sen dvdd2 sdi sck op[0] agnd2 vrlc/vbias vrx vrt vrb agnd1 avdd op[3]/sdo op[1] op[2] ordering information device temperature range package moisture sensitivity level peak soldering temperature wm8150cds 0 to 70 o c 20-pin ssop msl1 260 o c wm8150cds/r 0 to 70 o c 20-pin ssop (tape and reel) msl1 260 o c wm8150scds 0 to 70 o c 20-pin ssop (pb-free) msl1 260 o c wm8150scds/r 0 to 70 o c 20-pin ssop (pb-free, tape and reel) msl1 260 o c note: reel quantity = 2,000 wm8150 production data w pd rev 4.1 february 2005 4 pin description pin name type description 1 agnd2 supply analogue ground (0v). 2 dvdd1 supply digital core (logic and clock generator) supply (5v) 3 vsmp digital input video sample synchronisation pulse. 4 mclk digital input master clock. this clock is applied at n times the input pixel rate (n = 2, 3, 6, 8 or any multiple of 2 thereafter depending on input sample mode). 5 dgnd supply digital ground (0v). 6 sen digital input enables the serial interface when high. 7 dvdd2 supply digital supply (5v/3.3v), all digital i/o pins. 8 sdi digital input serial data input. 9 sck digital input serial clock. digital multiplexed output data bus. adc output data (d11:d0) is available in 4-bit multiplexed format as shown below. a b c d 10 op[0] digital output d8 d4 d0 ovrng 11 op[1] digital output d9 d5 d1 cc0 12 op[2] digital output d10 d6 d2 cc1 13 op[3]/sdo digital output d11 d7 d3 0 alternatively, pin op[3]/sdo may be used to output register read-back data when address bit 4=1 and sen has been pulsed high. see serial interface description in device description section for further details. 14 avdd supply analogue supply (5v) 15 agnd1 supply analogue ground (0v). 16 vrb analogue output lower reference voltage. this pin must be connected to agnd via a decoupling capacitor. 17 vrt analogue output upper reference voltage. this pin must be connected to agnd via a decoupling capacitor. 18 vrx analogue output input return bias voltage. this pin must be connected to agnd via a decoupling capacitor. 19 vrlc/vbias analogue i/o selectable analogue output voltage for rlc or single-ended bias reference. this pin would typically be connected to agnd via a decoupling capacitor. vrlc can be externally driven if programmed hi-z. 20 vinp analogue input video input. production data wm8150 w pd rev 4.1 february 2005 5 absolute maximum ratings absolute maximum ratings are stress ratings only. permanent damage to the device may be caused by continuously operating at or beyond these limits. device functional operating limits and guaranteed performance specifications are given under electrical characteristics at the test conditions specified. esd sensitive device. this device is manufactured on a cmos process. it is therefore generically susceptible to damage from excessive static voltages. proper esd precautions must be taken during handling and storage of this device. wolfson tests its package types according to ipc/jedec j-std-020b for moisture sensitivity to determine acceptable storage conditions prior to surface mount assembly. these levels are: msl1 = unlimited floor life at <30 c / 85% relative humidity. not normally stored in moisture barrier bag. msl2 = out of bag storage for 1 year at <30 c / 60% relative humidity. supplied in moisture barrier bag. msl3 = out of bag storage for 168 hours at <30 c / 60% relative humidity. supplied in moisture barrier bag. the moisture sensitivity level for each package type is specified in ordering information. condition min max analogue supply voltage: avdd gnd - 0.3v gnd + 7v digital core voltage: dvdd1 gnd - 0.3v gnd + 7v digital io supply voltage: dvdd2 gnd - 0.3v gnd + 7v digital ground: dgnd gnd - 0.3v gnd + 0.3v analogue grounds: agnd1 ? 2 gnd - 0.3v gnd + 0.3v digital inputs, digital outputs and digital i/o pins gnd - 0.3v dvdd2 + 0.3v analogue input (vinp) gnd - 0.3v avdd + 0.3v other pins gnd - 0.3v avdd + 0.3v operating temperature range: t a 0 c +70 c storage temperature after soldering -65 c +150 c notes: 1. gnd denotes the voltage of any ground pin. 2. agnd1, agnd2 and dgnd pins are intended to be operated at the same potential. differential voltages between these pins will degrade performance. recommended operating conditions condition symbol min typ max units operating temperature range t a 0 70 c analogue supply voltage avdd 4.75 5.0 5.25 v digital core supply voltage dvdd1 4.75 5.0 5.25 v 5v i/o dvdd2 4.75 5.0 5.25 v digital i/o supply voltage 3.3v i/o dvdd2 2.97 3.3 3.63 v wm8150 production data w pd rev 4.1 february 2005 6 electrical characteristics test conditions avdd = dvdd1 = 5.0v, dvdd2 = 3.3v, agnd = dgnd = 0v, t a = 25 c, mclk = 16mhz unless otherwise stated. parameter symbol test conditions min typ max unit overall system specification (including 12-bit adc, pga, offset and cds functions) full-scale input voltage range (see note 1) max gain min gain 0.30 3.22 vp-p vp-p input signal limits (see note 2) v in 0 vdd v full-scale transition error gain = 0db; pga[7:0] = 07(hex) -50 10 +50 mv zero-scale transition error gain = 0db; pga[7:0] = 07(hex) -50 10 +50 mv differential non-linearity dnl 0.5 1 lsb integral non-linearity inl 2 5 lsb total output noise min gain max gain 0.25 0.70 lsb rms lsb rms references upper reference voltage vrt 2.70 v lower reference voltage vrb 1.45 v input return bias voltage vrx 1.55 1.65 1.75 v diff. reference voltage (vrt-vrb) v rtb 1.15 1.25 1.35 v output resistance vrt, vrb, vrx 1 ? vrlc/reset-level clamp (rlc) rlc switching impedance 20 50 100 ? vrlc short-circuit current 1.86 2 4.5 ma vrlc output resistance 2 ? vrlc hi-z leakage current vrlc = 0 to avdd 1 a rlcdac resolution 4 bits rlcdac step size, rlcdac = 0 v rlcstep avdd = 5.0v 0.23 0.25 0.27 v/step rlcdac step size, rlcdac = 1 v rlcstep 0.14 0.16 0.20 v/step rlcdac output voltage at code 0(hex), rlcdacrng = 0 v rlcbot avdd = 5.0v 0.34 0.39 0.44 v rlcdac output voltage at code 0(hex), rlcdacrng = 1 v rlcbot 0.20 0.26 0.31 v rlcdac output voltage at code f(hex) rlcdacrng, = 0 v rlctop avdd = 5.0v 4.0 4.16 4.3 v rlcdac output voltage at code f(hex), rlcdacrng = 1 v rlctop 2.56 2.66 2.76 v offset dac, monotonicity guaranteed resolution 8 bits differential non-linearity dnl 0.1 0.5 lsb integral non-linearity inl 0.25 1 lsb step size 2.04 mv/step output voltage code 00(hex) code ff(hex) -247 +247 -260 +260 -273 +273 mv mv notes: 1. full-scale input voltage denotes the peak input signal amplitude that can be gained to match the adc input range. 2. input signal limits are the limits within which the full-scale input voltage signal must lie. production data wm8150 w pd rev 4.1 february 2005 7 test conditions avdd = dvdd1 = 5.0v, dvdd2 = 3.3v, agnd = dgnd = 0v, t a = 25 c, mclk = 16mhz unless otherwise stated. parameter symbol test conditions min typ max unit programmable gain amplifier resolution 8 bits gain equation 255 7.57 0] : pga[7 0.78 + v/v max gain g max 6.8 8.35 8.7 v/v min gain g min 0.75 0.78 0.82 v/v gain error 1 2 % internal channel offset v off 10 mv analogue to digital converter resolution 12 bits maximum speed 8 msps full-scale input range (2*(vrt-vrb)) v fs 2.5 v digital specifications digital inputs high level input voltage v ih 0.8 ? dvdd2 v low level input voltage v il 0.2 ? dvdd2 v high level input current i ih 1 a low level input current i il 1 a input capacitance c i 5 pf digital outputs high level output voltage v oh i oh = 1ma dvdd2 - 0.5 v low level output voltage v ol i ol = 1ma 0.5 v supply currents total supply current ? active 35 45 ma total analogue avdd, supply current ? active i avdd 30 40 ma total digital core, dvdd1, supply current ? active i dvdd1 1.7 2 ma digital i/o supply current, dvdd2 ? active (see note 3) i dvdd2 4 5 ma supply current ? full power down mode 300 400 a notes: 3. digital i/o supply current depends on the capacitive load attached to the pin. the digital i/o supply current is measured with approximately 50pf attached to the pin. wm8150 production data w pd rev 4.1 february 2005 8 input video sampling mclk vsmp input video t per t vsmpsu t vsmph t vsu t vh t rsu t rh t mclkl t mclkh figure 1 input video timing note: 1. see page 15 (programmable vsmp detect circuit) for video sampling description. test conditions vdd = 5.0v, dvdd = 3.3v, agnd = dgnd = 0v, t a = 25 c, mclk = 16mhz unless otherwise stated. parameter symbol test conditions min typ max units mclk period t per 62.5 ns mclk high period t mclkh 28.1 ns mclk low period t mclkl 28.1 ns vsmp set-up time t vsmpsu 8 ns vsmp hold time t vsmph 4 ns video level set-up time t vsu 15 ns video level hold time t vh 5 ns reset level set-up time t rsu 15 ns reset level hold time t rh 5 ns notes: 1. t vsu and t rsu denote the set-up time required after the input video signal has settled. 2. parameters are measured at 50% of the rising/falling edge. output data timing mclk op[3:0] t pd t pd figure 2 output data timing test conditions vdd = 5.0v, dvdd = 3.3v, agnd = dgnd = 0v, t a = 25 c, mclk = 16mhz unless otherwise stated. parameter symbol test conditions min typ max units output propagation delay t pd i oh = 1ma, i ol = 1ma 30 ns production data wm8150 w pd rev 4.1 february 2005 9 serial interface sck sdi sen sdo t sper t sckl t sckh t ssu t sh t sce t sew t sec t serd t scrd msb lsb t scrdz adc data adc data register data figure 3 serial interface timing test conditions vdd = 5.0, dvdd = 3.3v, agnd = dgnd = 0v, t a = 25 c, mclk = 16mhz unless otherwise stated. parameter symbol test conditions min typ max units sck period t sper 83.3 ns sck high t sckh 37.5 ns sck low t sckl 37.5 ns sdi set-up time t ssu 10 ns sdi hold time t sh 10 ns sck to sen set-up time t sce 20 ns sen to sck set-up time t sec 20 ns sen pulse width t sew 50 ns sen low to sdo = register data t serd 35 ns sck low to sdo = register data t scrd 35 ns sck low to sdo = adc data t scrdz 25 ns note: 1. parameters are measured at 50% of the rising/falling edge wm8150 production data w pd rev 4.1 february 2005 10 device description introduction a block diagram of the device showing the signal path is presented on page 1. the wm8150 processes the sampled video signal on vinp with respect to the video reset level or an internally/externally generated reference level through the analogue processing channel. this processing channel consists of an input sampling block with optional reset level clamping (rlc) and correlated double sampling (cds), an 8-bit programmable offset dac and an 8-bit programmable gain amplifier (pga). the adc then converts each resulting analogue signal to a 12-bit digital word. the digital output from the adc is presented on a 4-bit wide bus. on-chip control registers determine the configuration of the device, including the offsets and gains applied to each channel. these registers are programmable via a serial interface. input sampling the wm8150 has a single analogue processing channel and adc which can be used in a flexible manner to process both monochrome and line-by-line colour inputs. monochrome: vinp is sampled, processed by the analogue channel, and converted by the adc. the same offset dac and pga register values are always applied. colour line-by-line: vinp is sampled and processing by the analogue channel before being converted by the adc. the gains and offset register values applied to the pga and offset dac can be switched between the independent red, green and blue digital registers (e.g. red green blue red?) at the start of each line in order to facilitate line-by-line colour operation. the intm[1:0] bits determine which register contents are applied (see table 1) to the pga and offset dac. by using the intm[1:0] bits to select the desired register values only one register write is required at the start of each new colour line. reset level clamping (rlc) to ensure that the signal applied to the wm8150 vinp pin lies within the valid input range (0v to vdd) the ccd output signal is usually level shifted by coupling through a capacitor, c in. when active, the rlc circuit clamps the wm8150 side of this capacitor to a suitable voltage during the ccd reset period. the rlcint register bit controls is used to activate the reset level clamp circuit. a typical input configuration is shown in figure 4. the timing control block generates an internal clamp pulse, cl, from mclk and vsmp (when rlcint is high). when cl is active the voltage on the wm8150 side of c in , at vinp, is forced to the vrlc/vbias voltage (v vrlc ) by closing of switch 1. when the cl pulse turns off switch 1 opens, the voltage at vinp initially remains at v vrlc but any subsequent variation in sensor voltage (from reset to video level) will couple through c in to vinp. rlc is compatible with both cds and non-cds operating modes, as selected by switch 2. refer to the cds/non-cds processing section. production data wm8150 w pd rev 4.1 february 2005 11 timing control s/h 4-bit rlc dac cl + + - to offset dac rlc cds from control interface s/h v s r s from control interface mclk vsmp input sampling block cds c in vinp vrlc/ vbias 2 1 external vrlc vrlcext figure 4 reset level clamping and cds circuitry reset level clamping is controlled by register bit rlcint. figure 5 illustrates the effect of the rlcint bit for a typical ccd waveform, with cl applied during the reset period. the rlcint register bit is sampled on the positive edge of mclk that occurs during each vsmp pulse. the sampled level, high (or low) controls the presence (or absence) of the internal cl pulse on the next reset level. the position of cl can be adjusted by using control bits cdsref[1:0] (figure 6). mclk vsmp acyc/rlc or rlcint cl (cdsref = 01) input video 1x x 0x x 0 rgb rgb no rlc on this pixel rlc on this pixel programmable delay rgb figure 5 relationship of rlcint, mclk and vsmp to internal clamp pulse, cl the vrlc/vbias pin can be driven internally by a 4-bit dac (rlcdac) by writing to control bits rlcv[3:0]. the rlcdac range and step size may be increased by writing to control bit rlcdacrng. alternatively, the vrlc/vbias pin can be driven externally by writing to control bit vrlcext to disable the rlcdac and then applying a d.c. voltage to the pin. cds/non-cds processing for ccd type input signals, the signal may be processed using cds, which will remove pixel-by-pixel common mode noise. for cds operation, the video level is processed with respect to the video reset level, regardless of whether rlc has been performed. to sample using cds, control bit cds must be set to 1 (default), this sets switch 2 into the position shown in figure 4 and causes the signal reference to come from the video reset level. the time at which the reset level is sampled, by clock r s /cl, is adjustable by programming control bits cdsref[1:0], as shown in figure 6. wm8150 production data w pd rev 4.1 february 2005 12 mclk vsmp vs r s /cl (cdsref = 00) r s /cl (cdsref = 01) r s /cl (cdsref = 10) r s /cl (cdsref = 11) figure 6 reset sample and clamp timing for cis type sensor signals, non-cds processing is used. in this case, the video level is processed with respect to the voltage on pin vrlc/vbias, generated internally or externally as described above. the vrlc/vbias pin is sampled by r s at the same time as v s samples the video level in this mode; non-cds processing is achieved by setting switch 2 in the lower position, cds = 0. offset adjust and programmable gain the output from the cds block is a differential signal, which is added to the output of an 8-bit offset dac to compensate for offsets and then amplified by an 8-bit pga. the gain and offset can be set for each of three colours by writing to control bits dacx[7:0] and pgax[7:0] (where x can be r, g or b). in colour line-by-line mode the gain and offset coefficients that are applied to the pga and offset dac can be multiplexed by control of the intm[1:0] bits as shown in table 1. intm[1:0] description 00 red offset and gain registers are applied to offset dac and pga (dacr[7:0] and pgar[7:0]) 01 green offset and gain registers applied to offset dac and pga (dacg[7:0] and pgag[7:0]) 10 blue offset and gain registers applied to offset dac and pga (dacb[7:0] and pgab[7:0]) 11 reserved. table 1 offset dac and pga register control the gain characteristic of the wm8150 pga is shown in figure 7. figure 8 shows the maximum input voltage (at vinp) that can be gained up to match the adc full-scale input range (2.5v). 0 1 2 3 4 5 6 7 8 9 0 64 128 192 256 gain register value, pga[7:0] pga gain v/v 0 0.5 1 1.5 2 2.5 3 3.5 0 64 128 192 256 gain register value, pga[7:0] peak input voltage to match adc full-scale range figure 7 pga gain characteristic figure 8 peak input voltage to match adc full-scale range production data wm8150 w pd rev 4.1 february 2005 13 adc input black level adjust the output from the pga should be offset to match the full-scale range of the adc (v fs = 2.5v). for negative-going input video signals, a black level (zero differential) output from the pga should be offset to the top of the adc range by setting register bits pgafs[1:0]=10. for positive going input signal the black level should be offset to the bottom of the adc range by setting pgafs[1:0]=11. bipolar input video is accommodated by setting pgafs[1:0]=00 or pgafs[1:0]=01 (zero differential input voltage gives mid-range adc output). overall signal flow summary figure 9 represents the processing of the video signal through the wm8150. figure 9 overall signal flow the input sampling block produces an effective input voltage v 1 . for cds, this is the difference between the input video level v in and the input reset level v reset . for non-cds this is the difference between the input video level v in and the voltage on the vrlc/vbias pin, v vrlc , optionally set via the rlc dac. the offset dac block then adds the amount of fine offset adjustment required to move the black level of the input signal towards 0v, producing v 2 . the pga block then amplifies the white level of the input signal to maximise the adc range, outputting voltage v 3 . the adc block then converts the analogue signal, v 3 , to a 12-bit unsigned digital output, d 1 . the digital output is then inverted, if required, through the output invert block to produce d 2. calculating output for any given input the following equations describe the processing of the video and reset level signals through the wm8150. the values of v 1 , v 2 and v 3 are often calculated in reverse order during device setup. the pga value is written first to set the input voltage range, the offset dac is then adjusted to compensate for any black/reset level offsets and finally the rlc dac value is set to position the reset level correctly during operation. note: refer to wan0123 for detailed information on device calibration procedures. input sampling block: input sampling and referencing if cds = 1, (i.e. cds operation) the previously sampled reset level, v reset , is subtracted from the input video. v 1 = v in - v reset ................................................................... eqn. 1 if cds = 0, (non-cds operation) the simultaneously sampled voltage on pin vrlc is subtracted instead. v 1 = v in - v vrlc .................................................................... eqn. 2 if vrlcext = 1, v vrlc is an externally applied voltage on pin vrlc/vbias. if vrlcext = 0, v vrlc is the output from the internal rlc dac. v reset v vrlc v 3 cds = 1 cds = 0 vrlcext=1 260mv*(dac[7:0]-127.5)/127.5 analog - x + + v rlcstep *rlcv[3:0] + v rlcbot op[3:0] d 1 digital adc block pga block offset dac block input sampling block d 2 cds, vrlcext,rlcv[3:0], dac[7:0], pga[7:0], pgafs[1:0] and invop are set by programming internal control registers. cds=1 for cds, 0 for non-cds v in is vinp volta g e sampled on video sample v reset is v inp sampled during reset clamp v vrlc is voltage applied to vrlc pin v in x ( 4095/v fs ) +0 if pgafs[1:0]=11 +4095 if pgafs[1:0]=10 +2047 if pgafs[1:0]=0x pga g ain a = 0.78+(pga[7:0]*7.57)/255 output invert block d2 = d1 if invop = 0 d2 =4095-d1 if invop = 1 offset dac rlc dac + v 2 v 1 vrlcext=0 wm8150 production data w pd rev 4.1 february 2005 14 v vrlc = (v rlcstep ? rlcv[3:0]) + v rlcbot ................................. eqn. 3 v rlcstep is the step size of the rlc dac and v rlcbot is the minimum output of the rlc dac. offset dac block: offset (black-level) adjust the resultant signal v 1 is added to the offset dac output. v 2 = v 1 + {260mv ? (dac[7:0]-127.5) } / 127.5 ..................... eqn. 4 pga node: gain adjust the signal is then multiplied by the pga gain, v 3 = v 2 ? [0.78+(pga[7:0]*7.57)/255] ................................... eqn. 5 adc block: analogue-digital conversion the analogue signal is then converted to a 12-bit unsigned number, with input range configured by pgafs[1:0]. d 1 [11:0] = int{ ( v 3 /v fs ) ? 4095} + 2047 pgafs[1:0] = 00 or 01 ...... eqn. 6 d 1 [11:0] = int{ ( v 3 /v fs ) ? 4095} pgafs[1:0] = 11 ............... eqn. 7 d 1 [11:0] = int{ ( v 3 /v fs ) ? 4095} + 4095 pgafs[1:0] = 10 ............... eqn. 8 where the adc full-scale range, v fs = 2.5v if d 1 [11:0] < 0 d 1 [11:0] = 0 if d 1 [11:0] > 4095 d 1 [11:0] = 4095 output invert block: polarity adjust the polarity of the digital output may be inverted by control bit invop. d 2 [11:0] = d 1 [11:0] (invop = 0) ...................... eqn. 9 d 2 [11:0] = 4095 ? d 1 [11:0] (invop = 1) ...................... eqn. 10 production data wm8150 w pd rev 4.1 february 2005 15 output data format the digital data output from the adc is available to the user in 4-bit wide multiplexed. latency of valid output data with respect to vsmp is programmable by writing to control bits del[1:0]. the latency for each mode is shown in the operating mode timing diagrams section. figure 10 shows the output data formats for mode 1 and 3 ? 6. figure 11 shows the output data formats for mode 2. table 2 summarises the output data obtained for each format. mclk 4+4+4-bit output ab cd mclk 4+4+4-bit output d ab c d ab figure 10 output data formats (modes 1, 3, 4) figure 11 output data formats (mode 2) output format output pins output 4+4+4+4-bit (nibble) op[3:0] a = d11, d10, d9, d8 b = d7, d6, d5, d4 c = d3, d2, d1, d0 d = 0, cc[1], cc[0], ovrng table 2 details of output data shown in figure 10 and figure 11. flags the ovrng flag that is output during nibble d indicates that the current output data was produced by an input signal that exceeded the input range limit of the device. 1 = out of range, 0 = within range. the cc[1:0] flags that are output during nibble d are used to indicate which set of offset and gain registers have been used for the current data. cc[1:0] = 00 indicates red, cc[1:0] = 01 indicates green and cc[1:0] = 10 indicates that the blue offset and gain registers were applied during the processing. wm8150 production data w pd rev 4.1 february 2005 16 control interface the internal control registers are programmable via the serial digital control interface. the register contents can be read back via the serial interface on pin op[3]/sdo. note: it is recommended that a software reset is carried out after the power-up sequence, before writing to any other register. this ensures that all registers are set to their default values (as shown in table 4). serial interface: register write figure 12 shows register writing in serial mode. three pins, sck, sdi and sen are used. a six-bit address (a5, 0, a3, a2, a1, a0) is clocked in through sdi, msb first, followed by an eight-bit data word (b7, b6, b5, b4, b3, b2, b1, b0), also msb first. each bit is latched on the rising edge of sck. when the data has been shifted into the device, a pulse is applied to sen to transfer the data to the appropriate internal register. note all valid registers have address bit a4 equal to 0 in write mode. sck sen sdi a5 0 a3a2a1a0b7b6b5b4b3b2b1b0 address data word figure 12 serial interface register write a software reset is carried out by writing to address ?000100? with any value of data, (i.e. data word = xxxxxxxx. serial interface: register read-back figure 13 shows register read-back in serial mode. read-back is initiated by writing to the serial bus as described above but with address bit a4 set to 1, followed by an 8-bit dummy data word. writing address (a5, 1, a3, a2, a1, a0) will cause the contents (d7, d6, d5, d4, d3, d2, d1, d0) of corresponding register (a5, 0, a3, a2, a1, a0) to be output msb first on pin sdo (on the falling edge of sck). note that pin sdo is shared with an output pin, op[3], so no data can be read when reading from a register. the next word may be read in to sdi while the previous word is still being output on sdo. sck sen sdi a51a3a2a1a0xxxxxxxx address data word d7 d6 d5 d4 d3 d2 d1 d0 output data word sdo figure 13 serial interface register read-back timing requirements to use this device a master clock (mclk) of up to 16mhz and a per-pixel synchronisation clock (vsmp) of up to 8mhz are required. these clocks drive a timing control block, which produces internal signals to control the sampling of the video signal. mclk to vsmp ratios and maximum sample rates for the various modes are shown in table 3. production data wm8150 w pd rev 4.1 february 2005 17 programmable vsmp detect circuit the vsmp input is used to determine the sampling point and frequency of the wm8150. under normal operation a pulse of 1 mclk period should be applied to vsmp at the desired sampling frequency (as shown in the operating mode timing diagrams) and the input sample will be taken on the first rising mclk edge after vsmp has gone low. however, in certain applications such a signal may not be readily available. the programmable vsmp detect circuit in the wm8150 allows the sampling point to be derived from any signal of the correct frequency, such as a ccd shift register clock, when applied to the vsmp pin. when enabled, by setting the vsmpdet control bit, the circuit detects either a rising or falling edge (determined by posnneg control bit) on the vsmp input pin and generates an internal vsmp pulse. this pulse can optionally be delayed by a number of mclk periods, specified by the vdel[2:0] bits. figure 14 shows the internal vsmp pulses that can be generated by this circuit for a typical clock input signal. the internal vsmp pulse is then applied to the timing control block in place of the normal vsmp pulse provided from the input pin. the sampling point then occurs on the first rising mclk edge after this internal vsmp pulse, as shown in the operating mode timing diagrams. mclk vsmp (vdel = 000) intvsmp posnneg = 1 (vdel = 001) intvsmp (vdel = 010) intvsmp (vdel = 011) intvsmp (vdel = 100) intvsmp (vdel = 101) intvsmp (vdel = 110) intvsmp (vdel = 111) intvsmp posnneg = 0 (vdel = 000) intvsmp (vdel = 001) intvsmp (vdel = 010) intvsmp (vdel = 011) intvsmp (vdel = 100) intvsmp (vdel = 101) intvsmp (vdel = 110) intvsmp (vdel = 111) intvsmp input pins v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s v s figure 14 internal vsmp pulses generated by programmable vsmp detect circuit wm8150 production data w pd rev 4.1 february 2005 18 references the adc reference voltages are derived from an internal bandgap reference, and buffered to pins vrt and vrb, where they must be decoupled to ground. pin vrx is driven by a similar buffer, and also requires decoupling. the output buffer from the rlcdac also requires decoupling at pin vrlc/vbias when this is configured as an output. power supply the wm8150 can run from a 5v single supply or from split 5v (core) and 3.3v (digital interface) supplies. power management power management for the device is performed via the control interface. the device can be powered on or off completely by setting the en bit low. all the internal registers maintain their previously programmed value in power down mode and the control interface inputs remain active. operating modes table 3 summarises the most commonly used modes, the clock waveforms required and the register contents required for cds and non-cds operation. mode description cds available max sample rate timing requirements register contents with cds register contents without cds 1 monochrome/ colour line-by-line yes 2.67msps mclk max = 16mhz mclk:vsmp ratio is 6:1 setreg1: 0f(hex) setreg1: 0d(hex) 2 fast monochrome/ colour line-by-line yes 5.33msps mclk max = 16mhz mclk:vsmp ratio is 3:1 identical to mode 1 plus setreg3: bits 5:4 must be set to 0(hex) identical to mode 1 3 maximum speed monochrome/ colour line-by-line no 8msps mclk max = 16mhz mclk:vsmp ratio is 2:1 cds not possible setreg1: 4d(hex) 4 slow monochrome/ colour line-by-line yes 2msps mclk max = 16mhz mclk:vsmp ratio is 2n:1, n 4 identical to mode 1 identical to mode 1 table 3 wm8150 operating modes production data wm8150 w pd rev 4.1 february 2005 19 operating mode timing diagrams the following diagrams show 4-bit multiplexed output data and mclk, vsmp and input video requirements for operation of the most commonly used modes as shown in table 3. the diagrams are identical for both cds and non-cds operation. mclk vsmp vinp op[3:0] (del = 00) op[3:0] (del = 01) op[3:0] (del = 10) op[3:0] (del = 11) 16.5 mclk periods a b c d a b c d a b c d a b c d a b c d a b c a b c a b c d a b c d a b c a b c a b c a b c d a b c d a b c d a b c d a b c d d d d a b c d d d d d figure 15 mode 1 operation mclk vsmp (del = 00) vinp op[3:0] (del = 01) op[3:0] (del = 10) op[3:0] (del = 11) 23.5 mclk periods c d a b a b c d a b a b c d a b a b c d a b a b c d a b a b c d a b a b c d a b a b c d a b a b c d a b a b c d a b a b c d a b a b c d a b a b c d op[3:0] c d a b a b c d a b a b c d a b a b c d a b a b c d a b a b c d a b a b c d a b a b c d a b a b c d a b a b c d a b a b c d a b a b c d a b a b c d c d a b a b c d a b a b c d a b a b c d a b a b c d a b a b c d a b a b c d a b a b c d a b a b c d a b a b c d a b a b c d a b a b c d c d a b a b c d a b a b c d a b a b c d a b a b c d a b a b c d a b a b c d a b a b c d a b a b c d a b a b c d a b a b c d c d a b a b c d a b a b c d a b a b figure 16 mode 2 operation wm8150 production data w pd rev 4.1 february 2005 20 mclk vsmp vinp op[3:0] (del = 00) 16.5 mclk periods op[3:0] (del = 01) op[3:0] (del = 10) op[3:0] (del = 11) a b c d a b c d a b c d a b c d a b c d a b c d a b c d a b c d a b c d a b c d a b c d a b c d a b c d a b c d a b c d a b c d a b c d a b c d a b c d a b c d a b c d a b c d a b c d a b c d a b c d a b c d a b c d a b c d a b c d a b c d a b c d a b c d a b c d a b c d a b c d a b c d a b c d a b c d a b c d a b c d a b c d a b c d a b c d a b c d a b c d a b c d a b c d a b c d a b c d a b c d a b c d a b c d figure 17 mode 3 operation 16.5 mclk periods mclk vsmp vinp op[3:0] (del = 00) op[3:0] (del = 01) op[3:0] (del = 10) op[3:0] (del = 11) a b c a b c a b c d a b c a b c a b c d a b c a b c a b c d a b c a b c a b c a b c d d d d d d d d d d d d d figure 18 mode 4 operation (mclk:vsmp ratio = 8:1) production data wm8150 w pd rev 4.1 february 2005 21 device configuration register map the following table describes the location of each control bit used to determine the operation of the wm8150. the register map is programmed by writing the required codes to the appropriate addresses via the serial interface. bit address wm8150 production data w pd rev 4.1 february 2005 22 register map description the following table describes the function of each of the control bits shown in table 4. register bit no bit name(s) default description 0 en 1 0 = complete power down, 1 = fully active. 1 cds 1 select correlated double sampling mode: 0 = single ended mode, 1 = cds mode. offsets pga output to optimise the adc range for different polarity sensor output signals. zero differential pga input signal gives: 5:4 pgafs[1:0] 00 00 = zero output (use for bipolar video) 01 = zero output 10 = full-scale positive output (use for negative going video) 11 = full-scale negative output (use for positive going video) setup register 1 6 mode3 0 required when operating in mode3: 0 = other modes, 1 = mode3. 2 invop 0 digitally inverts the polarity of output data. 0 = negative going video gives negative going output, 1 = negative-going video gives positive going output data. 3 vrlcext 0 when set powers down the rlcdac, changing its output to hi-z, allowing vrlc/vbias to be externally driven. 5 rlcdacrng 1 sets the output range of the rlcdac. 0 = rlcdac ranges from 0 to vdd (approximately), 1 = rlcdac ranges from 0 to vrt (approximately). sets the output latency in adc clock periods. 1 adc clock period = 2 mclk periods except in mode 2 where 1 adc clock period = 3 mclk periods. setup register 2 7:6 del[1:0] 00 00 = minimum latency 01 = delay by one adc clock period 10 = delay by two adc clock periods 11 = delay by three adc clock periods 3:0 rlcv[3:0] 1111 controls rlcdac driving vrlc pin to define single ended signal reference voltage or reset level clamp voltage. see electrical characteristics section for ranges. cds mode reset timing adjust. setup register 3 5:4 cdsref[1:0] 01 00 = advance 1 mclk period 01 = normal 10 = retard 1 mclk period 11 = retard 2 mclk periods software reset any write to software reset causes all cells to be reset. it is recommended that a software reset be performed after a power-up before any other register writes. 3 rlcint 0 this bit is used to determine whether reset level clamping is enabled. 0 = rlc disabled, 1 = rlc enabled. setup register 4 5:4 intm[1:0] 00 colour selection bits used in internal modes. 00 = red, 01 = green, 10 = blue and 11 = reserved. see table 1 for details. production data wm8150 w pd rev 4.1 february 2005 23 register bit no bit name(s) default description 0 vsmpdet 0 0 = normal operation, signal on vsmp input pin is applied directly to timing control block. 1 = programmable vsmp detect circuit is enabled. an internal synchronisation pulse is generated from signal applied to vsmp input pin and is applied to timing control block. 3:1 vdel[2:0] 000 when vsmpdet = 0 these bits have no effect. when vsmpdet = 1 these bits set a programmable delay from the detected edge of the signal applied to the vsmp pin. the internally generated pulse is delayed by vdel mclk periods from the detected edge. see figure 14, internal vsmp pulses generated for details. setup register 5 4 posnneg 0 when vsmpdet = 0 this bit has no effect. when vsmpdet = 1 this bit controls whether positive or negative edges are detected: 0 = negative edge on vsmp pin is detected and used to generate internal timing pulse. 1 = positive edge on vsmp pin is detected and used to generate internal timing pulse. see figure 14 for further details. 0 = normal operation, op[3:0] output adc data. 1 = internal clock test mode. this allows internal timing signals to be multiplexed onto the op[3:0] pins as follows. pin tclk=0 tclk=1 op[3] op[3] intvsmp op[2] op[2] video sample clock op[1] op[1] adc clock test register 1 7 tclk 0 op[0] op[0] reset sample clock offset dac (red) 7:0 dacr[7:0] 80 red channel offset dac value. used under control of the intm[1:0] control bits. offset dac (green) 7:0 dacg[7:0] 80 green channel offset dac value. used under control of the intm[1:0] control bits. offset dac (blue) 7:0 dacb[7:0] 80 blue channel offset dac value. used under control of the intm[1:0] control bits. offset dac (rgb) 7:0 dac[7:0] a write to this register location causes the red, green and blue offset dac registers to be overwritten by the new value pga gain (red) 7:0 pgar[7:0] 0 determines the gain of the red channel pga according to the equation: red channel pga gain = [0.78+(pgar[7:0]*7.57)/255]. used under control of the intm[1:0] control bits. pga gain (green) 7:0 pgag[7:0] 0 determines the gain of the green channel pga according to the equation: green channel pga gain = [0.78+(pgag[7:0]*7.57)/255]. used under control of the intm[1:0] control bits. pga gain (blue) 7:0 pgab[7:0] 0 determines the gain of the blue channel pga according to the equation: blue channel pga gain = [0.78+(pgab[7:0]*7.57)/255]. used under control of the intm[1:0] control bits. pga gain (rgb) 7:0 pga[7:0] a write to this register location causes the red, green and blue pga gain registers to be overwritten by the new value table 5 register control bits wm8150 production data w pd rev 4.1 february 2005 24 recommended external components dvdd2 agnd1 vinp mclk vsmp sck sen sdi op[0] op[1] op[2] op[3]/sdo vrlc/vbias vrx vrt vrb avdd c1 c6 c8 c4 c5 c7 c9 avdd video input timing signals interface controls output data bus dgnd agnd agnd agnd dgnd c3 agnd agnd2 c10 c12 avdd ++ dgnd agnd dvdd2 c11 + dgnd dvdd1 wm8150 c1-9 should be fitted as close to wm8150 as possible. notes: agnd and dgnd should be connected as close to wm8150 as possible. 1. 2. dvdd2 c2 dgnd dvdd1 dvdd1 figure 19 external components diagram component reference suggested value description c1 100nf de-coupling for dvdd2. c2 100nf de-coupling for dvdd1. c3 100nf de-coupling for avdd. c4 10nf high frequency de-coupling between vrt and vrb. c5 1 f low frequency de-coupling between vrt and vrb (non-polarised). c6 100nf de-coupling for vrb. c7 100nf de-coupling for vrx. c8 100nf de-coupling for vrt. c9 100nf de-coupling for vrlc. c10 10 f reservoir capacitor for dvdd2. c11 10 f reservoir capacitor for dvdd1. c12 10 f reservoir capacitor for avdd. table 6 external components descriptions production data wm8150 w pd rev 4.1 february 2005 25 package dimensions notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion, not to exceed 0.20mm. d. meets jedec.95 mo-150, variation = ae. refer to this specification for further details. dm0015.b ds: 20 pin ssop (7.2 x 5.3 x 1.75 mm) symbols dimensions (mm) min nom max a ----- ----- 2.0 a 1 0.05 ----- ----- a 2 1.65 1.75 1.85 b 0.22 0.30 0.38 c 0.09 ----- 0.25 d 6.90 7.20 7.50 e 0.65 bsc e 7.40 7.80 8.20 5.00 5.30 5.60 l 0.55 0.75 0.95 ref: a a2 a1 seating plane -c- 0.10 c 10 1 d 11 20 e b e1 e - jedec.95, mo 150 0 o 4 o 8 o e 1 l 1 0.125 ref c l gauge plane 0.25 l 1 wm8150 production data w pd rev 4.1 february 2005 26 important notice wolfson microelectronics plc (wm) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current. all products are sold subject to the wm terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. wm warrants performance of its products to the specifications applicable at the time of sale in accordance with wm?s standard warranty. testing and other quality control techniques are utilised to the extent wm deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. in order to minimise risks associated with customer applications, adequate design and operating safeguards must be used by the customer to minimise inherent or procedural hazards. wolfson products are not authorised for use as critical components in life support devices or systems without the express written approval of an officer of the company. life support devices or systems are devices or systems that are intended for surgical implant into the body, or support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided, can be reasonably expected to result in a significant injury to the user. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. wm assumes no liability for applications assistance or customer product design. wm does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of wm covering or relating to any combination, machine, or process in which such products or services might be or are used. wm?s publication of information regarding any third party?s products or services does not constitute wm?s approval, license, warranty or endorsement thereof. reproduction of information from the wm web site or datasheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. representation or reproduction of this information with alteration voids all warranties provided for an associated wm product or service, is an unfair and deceptive business practice, and wm is not responsible nor liable for any such use. resale of wm?s products or services with statements different from or beyond the parameters stated by wm for that product or service voids all express and any implied warranties for the associated wm product or service, is an unfair and deceptive business practice, and wm is not responsible nor liable for any such use. address: wolfson microelectronics plc westfield house 26 westfield road edinburgh eh11 2qb united kingdom tel :: +44 (0)131 272 7000 fax :: +44 (0)131 272 7001 email :: sales@wolfsonmicro.com |
Price & Availability of WM8150SCDSR
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |